The present invention relates to methods for biasing Voltage Controlled Oscillators, and in particular embodiments to biasing Voltage Controlled Oscillators such that the phase noise contributed by the biasing is reduced.
Voltage Controlled Oscillators (VCOs) are well-known. VCOs have been used in a wide variety of applications having different requirements. For example, VCOs are presently used in transceivers for wireless communications devices, such as cellular telephones, for generating a Local Oscillator (LO) signal that is mixed in a downconverter with an incoming RF signal to generate an Intermediate Frequency (IF) signal that is then further processed by downstream circuitry within the device. In general, it is desirable that the VCO generate an LO signal that has low phase noise. Phase noise is the noise-to-LO signal power ratio.
Presently available cellular systems utilize a variety of different air interfaces, including GSM (Global System for Mobile Communications), TDMA (Time Division Multiple Access), and CDMA (Code Division Multiple Access). In general, the LO phase noise requirement for CDMA cellular transceivers is much more stringent than the phase noise requirement for TDMA or GSM cellular transceivers. Low phase noise is also desirable for many other VCO applications, including, for example, optic receivers.
VCOs used in cellular transceivers and other applications require separate biasing circuitry, such as a current mirror and a bias current generator, in order to generate the bias current that is required to limit the current of the VCO core. However, such separate biasing circuitry introduces phase noise that is amplified by the current mirror ratio. The use of a low current mirror ratio (e.g., a 1:1 current mirror ratio) may improve phase noise performance, but at the expense of undesirably large power consumption by the biasing circuitry. Moreover, typical biasing circuitry includes some type of positive feedback, which also increases LO phase noise.
Presently available biasing schemes may provide adequate phase noise performance for certain applications, however many applications can benefit from improved. phase noise performance.
Based on the above, there presently exists a need in the art for a VCO that is biased in such a manner as to achieve superior phase noise performance in a power-efficient manner. The present invention addresses this and other needs in the art.
One aspect of the present invention encompasses a self-biased voltage controlled oscillator (VCO) that includes a VCO core including a plurality of switching transistors, a resonant tank circuit operatively coupled to the VCO core, a current source operatively coupled to the VCO core for supplying a bias current to the VCO core, and a biasing circuit operatively coupled to both the resonant tank circuit and to the current source. The biasing circuit and the switching transistors of the VCO core cooperatively function to bias the current source, whereby the VCO is self-biased.
According to another aspect of the present invention, the biasing circuit and the switching transistors of the VCO core, in combination, constitute a constant transconductance biasing circuit that controls the transconductance of the switching transistors of the VCO core.
In a first exemplary embodiment of the present invention, the current source is a PMOS transistor, the resonant tank circuit is an LC resonant tank circuit includes a pair of varactor diodes, and an inductor, arranged in parallel. A DC bias voltage is supplied to the central tap of the inductor. The switching transistors of the VCO core illustratively may include a first pair of cross-coupled PMOS transistors and a second pair of cross-coupled NMOS transistors. The LC resonant tank circuit illustratively may be arranged in parallel between the first and second pairs of cross-coupled CMOS transistors of the VCO core.
In the first exemplary embodiment, the biasing circuit includes an uppermost CMOS transistor having a first electrode coupled to the power supply voltage, a gate electrode coupled to the gate electrode of the current source, and a second electrode coupled to the gate electrodes of the uppermost CMOS transistor and the current source; an intermediate CMOS transistor having a first electrode coupled to the second electrode of the uppermost CMOS transistor, a gate electrode coupled to the second electrode of the current source, and a second electrode; a lowermost CMOS transistor having a first electrode coupled to the second electrode of the intermediate CMOS transistor, a second electrode coupled to ground, and a gate electrode coupled to a biasing point of the VCO core; and, a resistor connected between the second electrode of the lowermost CMOS transistor and ground.
In the first exemplary embodiment, the first pair of switching transistors of the VCO core includes a first PMOS transistor having a gate electrode, a first electrode coupled to a first node, and a second electrode coupled to a first terminal of the inductor, and a second PMOS transistor having a gate electrode coupled to the second electrode of the first PMOS transistor, a first electrode coupled to the first node, and a second electrode coupled to both a second terminal of the inductor and to the gate electrode of the first PMOS transistor. The second pair of switching transistors of the VCO core includes a first NMOS transistor having a gate electrode, a first electrode coupled to a second node, and a second electrode coupled to the first terminal of the inductor, and a second NMOS transistor having a gate electrode coupled to the second electrode of the first NMOS transistor, a first electrode coupled to the second node, and a second electrode coupled to both the second terminal of the inductor and to the gate electrode of the first NMOS transistor.
The first exemplary embodiment also includes a first inductor coupled between the second electrode of the current source and the first node, and a second inductor coupled between ground and the second node.
In a second exemplary embodiment of the present invention, the VCO further includes a first capacitor coupled between the second plate of the first varactor and the second electrode of the first NMOS transistor of the second pair of switching transistors of the VCO core; and, a second capacitor connected between the second plate of the second varactor and the second electrode of the second NMOS transistor of the second pair of switching transistors of the VCO core. The second exemplary embodiment further includes a first biasing resistor coupled between a first tank circuit node and a VCO frequency tuning voltage; and, a second biasing resistor coupled between a second tank circuit node and the VCO frequency tuning voltage. The first tank circuit node is between the first capacitor and the first varactor of the tank circuit, and the second tank circuit node is between the second capacitor and the second varactor of the tank circuit.